1. Field of the Invention
The present invention relates to a decoder circuit, and more particularly to a dynamic decoder which resists a noise from a power supply.
2. Description of the Related Art
A conventional dynamic decoder circuit, for example, having four input terminals is constituted as shown in FIG. 4. That is, the circuit includes a p-channel MOS transistor P.sub.1 having a source connected to a power supply VDD and a gate to which a precharging signal .PHI. is supplied through a buffer 1, and an n-channel MOS transistor N.sub.s having a source which is grounded and a gate to which the precharging signal .PHI. is supplied through the buffer 1. In this circuit, a MOS transistor train consisting of n-channel MOS transistors N.sub.1 to N.sub.4 which are connected to each other in series are inserted between a drain of the p-channel MOS transistor P.sub.1 and a drain of the n-channel MOS transistor Ns. Data signals D.sub.1 to D.sub.4 are supplied to gates G.sub.1 to G.sub.4 of the n-channel MOS transistors N.sub.1 to N.sub.4 through buffers 2 to 5, respectively. In such an arrangement, an output signal V.sub.out of the decoder circuit is obtained from the drain of the p-channel MOS transistor P.sub.1.
Subsequently, an operation of the decoder circuit will be described. At first, the precharging signal .PHI. is set to a L level. At this time, the buffer 1 makes ground potential inputted to the gate of the p-channel MOS transistor P.sub.1 as well as the gate of the n-channel MOS transistor N.sub.s. Therefore, the p-channel MOS transistor P.sub.1 brings into an on-state whereas the n-channel MOS transistor N.sub.2 brings into an off-state. As a result, the output signal V.sub.out becomes a potential of power supply regardless of the levels of the data signals D.sub.1 to D.sub.4 (hereinafter this state being referred to as "a precharging state").
Subsequently, the precharging signal .PHI. is changed into a H level. At this time, the buffer 1 makes power potential inputted to the gate of the p-channel MOS transistor P.sub.1 as well as the gate of the n-channel MOS transistor N.sub.s. As a result, the p-channel MOS transistor P.sub.1 is changed into the off-state whereas the n-channel MOS transistor N.sub.s is changed into the on-state. Therefore, the output signal V.sub.out depends on the levels of the data signals D.sub.1 to D.sub.4. That is, in the case where all of the data signals D.sub.1 to D.sub.4 are at the H level, since the buffers 2 to 5 output power potential, respectively, all of the n-channel MOS transistors N.sub.1 to N.sub.4 bring into the on-state, whereby the output signal V.sub.out outputs ground potential (hereinafter this state being referred to as "a sampling state"). On the other hand, if the levels of the data signals D.sub.1 to D.sub.4 are set in such a manner that D.sub.1, D.sub.2 and D.sub.3 are at the H level and D.sub.4 is at the L level, since the buffers 2 to 4 output power potential, the n-channel MOS transistors N.sub.1 to N.sub.3 bring into the on-state. However, the n-channel MOS transistor N.sub.4 brings into the off-state because the buffer 4 outputs ground potential. Hence, the output signal V.sub.out holds power potential, which is the output level in the precharging state, as it is (hereinafter this state being referred to as "a holding state").
By the way, in the above-mentioned conventional decoder circuit, there exist floating capacities C.sub.1 to C.sub.3 and C.sub.L irrelevant to the nodes of the n-channel MOS transistors N.sub.1 to N.sub.4 and output signal V.sub.out. An influence of those floating capacities C.sub.1 to C.sub.3 and C.sub.L on a signal outputted from the decoder when power potential fluctuates will be described below.
It is assumed that the data signals D.sub.1 to D.sub.4 are set such that D.sub.1 to D.sub.3 are at the H level but D.sub.4 is at the L level. In this case, the decoder circuit is changed from the precharging state to the holding state, and its timing chart is shown in FIG. 5. In the precharging state, when power potential VDD is V.sub.1, the respective gate potentials G.sub.1 to G.sub.4 for the n-channel MOS transistors N.sub.1 to N.sub.4 are so that G.sub.1 to G.sub.3 are V.sub.1 and G.sub.4 is 0. Since the p-channel MOS transistors N.sub.1 to N.sub.4 have a threshold value V.sub.TN, the respective nodes A to C have a level V.sub.1 -V.sub.TN.
Thereafter, the precharging signal is changed into the H level so that the decoder circuit comes to the holding state. At this time, because the p-channel MOS transistor P.sub.1 is in the off-state, the output signal V.sub.out is held to V.sub.1 by the floating capacity C.sub.L. At this time, a charge Q.sub.L of the floating capacity C.sub.L is equal to C.sub.L V.sub.1. On the other hand, the levels of the nodes A to C are held to V.sub.1 -V.sub.TN because the n-channel MOS transistor N.sub.4 is in the off-state. At this time, the charges Q.sub.1 to Q.sub.3 of the respective floating capacities C.sub.1 to C.sub.3 are represented as follows: EQU Q.sub.1 =C.sub.1 (V.sub.1 -V.sub.TN) EQU Q.sub.2 =C.sub.2 (V.sub.1 -V.sub.TN) EQU Q.sub.3 =C.sub.3 (V.sub.1 -V.sub.TN)
Here, it is assumed that the power potential VDD is changed from V.sub.1 to V.sub.2 where V2-V1.gtoreq.V.sub.TN. Although the source of the p-channel MOS transistor P.sub.1 is changed into V.sub.2 in level with fluctuation of power supply, the gate thereof is also changed into V.sub.2 in level by the aid of the buffer 1. The p-channel MOS transistor P.sub.1 is held in the off-state against fluctuation of power supply. On the other hand, the gate potential G.sub.1 to G.sub.3 for the n-channel MOS transistors N.sub.1 to N.sub.3 are moved to V.sub.2 in level by the aid of the buffers 2 and 3 likewise. At this time, because of G.sub.1 =V.sub.2 .gtoreq.V.sub.out +V.sub.TN =V.sub.1 +V.sub.TN, the node A rises up to the same level as the output signal V.sub.out. However, because the p-channel MOS transistor P.sub.1 is in the off-state, electric charges which are charged in the floating capacity C.sub.L result in transfer. That is, the charges are shared between the floating capacity C.sub.L and the floating capacities C.sub.1, C.sub.2 and C.sub.3, as a result of which the output signal V.sub.out is fluctuated as follows: EQU V.sub.out =V.sub.1 -{(C.sub.1 +C.sub.2 +C.sub.3)/(C.sub.1 +C.sub.2 +C.sub.3 +C.sub.L)}.multidot.V.sub.TN
Thereafter, even though power potential VDD is again returned to V.sub.1, the level of the output signal V.sub.out is held as it is. If C.sub.1+C.sub.2 +C.sub.3 =C.sub.L and VTM =V.sub.1 /2, then the following condition is satisfied. EQU V.sub.out .apprxeq.V.sub.1 -V.sub.TN =V.sub.1 /2
This means that, if a logical threshold value for a post-stage to which the output signal V.sub.out of the decoder circuit is inputted is VDD/2, the level of the output signal V.sub.out is logically inverted intentionally. That is, when the fluctuation of power supply exceeds V.sub.TN, the decoder circuit malfunctions.
As a first countermeasure against the above-described fluctuation of power supply, the floating capacity C.sub.L, which is set so as to satisfy the condition of C.sub.L .gtoreq.C.sub.1 +C.sub.2 +C.sub.3, is inserted into the decoder circuit as shown in FIG. 4. A timing chart at this case is shown in FIG. 6. Likewise in the above-described case, the charge sharing occurs against the fluctuation of power supply in the holding state. However, if C.sub.L =C.sub.1 +C.sub.2 +C.sub.3 and V.sub.TN =V.sub.1 /2, then the output signal V.sub.out can be set as follows: EQU V.sub.out =V.sub.1 -V.sub.TN /2=3/4 V.sub.1
Likewise in the foregoing case, if a logical threshold value for a post-stage to which the output signal V.sub.out of the decoder circuit is inputted is VDD/2, this makes it unnecessary to logically invert the level of the output signal V.sub.out.
Furthermore, as a second countermeasure against the fluctuation of power supply, there is a decoder circuit shown in FIG. 7. This decoder circuit includes a p-channel MOS transistor P.sub.1 having a source which is connected to a power supply VDD and a gate which inputs a precharging signal .PHI. through a buffer 11, and an n-channel MOS transistor N.sub.s having a source which is connected to ground potential and a gate to which the precharging signal .PHI. is inputted through the buffer 11. In the decoder circuit, a MOS transistor train consisting of n-channel MOS transistors N.sub.1 to N.sub.4 which are connected in series is inserted between the drain of the p-channel MOS transistor P.sub.1 and the drain of the n-channel MOS transistor N.sub.s. Data signals D.sub.1 to D.sub.4 are inputted to gates G.sub.1 to G.sub.4 of the n-channel MOS transistors N.sub.1 to N.sub.4 through 2-input type OR buffers 12 to 15, respectively. The precharging signal .PHI. is inversely inputted to one input terminal of each of the 2 -input type OR buffers 12 to 15. Also, one terminals of capacities C.sub.H1 to C.sub.H4 are connected to the gates G.sub.1 to G.sub.4, respectively, whereas the other terminals of the capacities C.sub.H1 to C.sub.H4 are commonly connected to each other, and input a step-up signal .PHI.' through a buffer 16. In this decoder circuit, an output signal V.sub.out is obtained from the drain of the p-channel MOS transistor P.sub.1.
Now, an operation of the decoder circuit thus organized will be described with reference to a timing chart shown in FIG. 8.
At first, when the precharging signal .PHI. is at the L level, the p-channel MOS transistor P.sub.1 is in an on-state and the output signal V.sub.out comes to a V.sub.1 level. Also, since the two-input type OR buffers 12 to 15 inversely input the precharging signal .PHI., they output a signal of the V.sub.1 level regardless of the levels of the data signals D.sub.1 to D.sub.4, respectively. Nodes A to C between the respective n-channel MOS transistors N.sub.1 to N.sub.4 are precharged up to the levels of V.sub.1 -V.sub.TN likewise in the decoder circuit shown in FIG. 4. Subsequently, when the step-up signal .PHI.' comes to the H level, the respective potentials of the gates G.sub.1 to G.sub.4 rises up to the level of 2 V.sub.1 due to C.sub.H1 to C.sub.H4. Hence, because of G.sub.1 =2 V.sub.1 .gtoreq.V.sub.out +V.sub.TN =3/2 V.sub.1, the potential of the node A rises up to the same level as the output signal V.sub.out. However, unlike the foregoing case, because the p-channel MOS transistor P.sub.1 is in the on-state, the potential of the node A rises up to the level of V.sub.1. Likewise, the potentials of the nodes B and C rise up to the level of V.sub.1. When the step-up signal .PHI.' comes to the L level, the levels of the gates G.sub.1 to G.sub.4 are changed into V.sub.1 again. However, the levels of the nodes A to C are not changed.
Then, when the precharging signal .PHI. comes to the H level, the p-channel MOS transistor P.sub.1 is changed into the off-state, and the gates G.sub.1 to G.sub.4 also come to the levels of the data signals D.sub.1 to D.sub.4, respectively. In FIG. 8, the data signals D.sub.1 to D.sub.3 are set to the H level whereas the data signal D.sub.4 is set to the L level, likewise in the foregoing case. Since the n-channel MOS transistor N.sub.4 is in the off-state, the output signal V.sub.out is held to the V.sub.1 level. At this time, it is assumed that the power potential VDD fluctuates from V.sub.1 to V.sub.2 (V.sub.2 .gtoreq.V.sub.1 +V.sub.TN). The gates G.sub.1 to G.sub.3 are changed from V.sub.1 to V.sub.2 with fluctuation of VDD. However, the electric charges in the floating capacities C.sub.1 to C.sub.3 and C.sub.L is not transferred anywhere. Hence, the condition of V.sub.out =V.sub.1 is held with no change in level of the output signal V.sub.out. That is, the decoder circuit does not malfunction against the fluctuation of power supply.
The conventional decoder circuit shown in FIG. 4 makes it necessary to increase the capacity C.sub.L. However, for that reason, it has a drawback that the reading speed is low in the sapling state.
On the other hand, the conventional decoder circuit shown in FIG. 7 has no drawback that the reading speed is low. However, it has a drawback that a lot of additional circuits such as the 2-input OR buffers and the capacities C.sub.H1 to C.sub.H4 as well as the control operation using the step-up signal .PHI.' are required for making the potentials of the gates G.sub.1 to G.sub.4 rise.